Multi-layer semiconductor package with stacked passive components

A semiconductor package comprising:

• a base layer including a leadframe and a base layer dielectric substrate filling gaps between elements of the leadframe;
• a first layer including a semiconductor die embedded within a second dielectric substrate, and a first set of metal pillars extending through the second dielectric substrate,
• wherein the first layer is stacked on the base layer such that the first set of metal pillars are electrically coupled to the elements of the leadframe;
• a second layer stacked on the first layer, the second layer including a metal trace patterned on the second dielectric substrate, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer;
• and
• a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars,
• wherein the inductor is exposed on an outer surface of the semiconductor package.

A method of making a semiconductor package, comprising:

• providing a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate;
• providing a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer;
• and
• providing a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

A method of making a semiconductor package comprising:

• providing a base layer including a leadframe and a base layer dielectric substrate filling gaps between elements of the leadframe;
• providing a first layer including a semiconductor die embedded within a second dielectric substrate, and a first set of metal pillars extending through the second dielectric substrate,
• wherein the first layer is stacked on the base layer such that the first set of metal pillars are electrically coupled to the elements of the leadframe;
• providing a second layer stacked on the first layer, the second layer including a metal trace patterned on the second dielectric substrate, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer;
• and
• providing a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars,
• wherein the inductor is exposed on an outer surface of the semiconductor package.