Semiconductor package

A semiconductor package comprising:

• a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer,
• wherein each of the redistribution patterns comprises a via portion, a pad portion, and a line portion that are connected to each other to form a single object,
• the pad portion vertically overlaps the via portion,
• the line portion extends from the pad portion,
• a level of a bottom surface of the pad portion is lower than a level of a bottom surface of the line portion,
• a side surface of the via portion has a linear shape, and
• a side surface of the pad portion has a rounded shape.

A semiconductor package comprising:

• a lower redistribution substrate including an insulating layer and first redistribution patterns in the insulating layer;
• a first semiconductor chip on the lower redistribution substrate, the first semiconductor chip comprising chip pads;
• first connection terminals being between and connecting the lower redistribution substrate and the chip pads of the first semiconductor chip;
• a mold layer on the lower redistribution substrate to cover the first semiconductor chip;
• metal pillars around the first semiconductor chip to penetrate the mold layer and connected to the lower redistribution substrate;
• and
• an upper redistribution substrate on the mold layer, the upper redistribution substrate comprising an upper insulating layer and an upper redistribution pattern on the upper insulating layer,
• wherein each of the first redistribution patterns comprises a first via portion, a first pad portion, and a first line portion that are connected to each other to form a single object,
• the first pad portion vertically overlaps with the first via portion,
• the first line portion extends from the first pad portion, and
• a level of a bottom surface of the first line portion is lowered with increasing a distance from a center portion of the first line portion in an outward direction.