US 2022/0037253 A1 · MEMORY CELL ARRAY, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF

Abstract

A tridimensional memory cell array includes vertically stacked first conductive lines, vertically stacked second conductive lines, and first and second flights of steps. First and second conductive lines extend along a first direction. The second conductive lines are disposed at a distance along a second direction from the first conductive lines. First and second directions are orthogonal. Along the first direction, the first flights are disposed at opposite ends of the first conductive lines and the second flights are disposed at opposite ends of the second conductive lines. The first and second flights include landing pads and connective lines alternately disposed along the first direction. The landing pads are wider than the connective lines along the second direction. Along the second direction, landing pads of the first flights face connective lines of the second flights and landing pads of the second flights face connective lines of the first flights.

Claims20

Dependent claims

A tridimensional memory cell array, comprising:

vertically stacked first conductive lines extending along a first direction;
vertically stacked second conductive lines extending along the first direction and disposed at a distance along a second direction from the first conductive lines, the second direction being orthogonal to the first direction;
first flights of steps disposed at opposite ends of the stacked first conductive lines along the first direction;
and
second flights of steps disposed at opposite ends of the stacked second conductive lines along the first direction,
wherein the first flights of steps and the second flights of steps comprise landing pads and connective lines alternately disposed along the first direction,
the landing pads are wider than the connective lines along the second direction,
the landing pads of the first flights of steps face the connective lines of the second flights of steps along the second direction, and
the landing pads of the second flights of steps face the connective lines of the first flights of steps along the second direction.

6 more elements

A semiconductor device, comprising:

driving circuitry and
tridimensionally arranged memory cells connected to the driving circuitry, wherein the tridimensionally arranged memory cells comprise:
first gate lines vertically stacked on each other;
first memory cell layers extending along a stacking direction of the first gate lines and contacting the first gate lines;
first source and drain lines extending along the stacking direction of the first gate lines and separated from the first gate lines along a first direction by at least one layer of the first memory cell layers;
first connective lines disposed in contact with the first gate lines at opposite sides of the first gate lines along a second direction;
first landing pads disposed in contact with the first connective lines along the second direction and wider than the first connective lines along the first direction;
second memory cell layers extending along the stacking direction of the first gate lines and disposed at an opposite side of the first source and drain lines along the first direction with respect to the first memory cell layers;
second gate lines, vertically stacked on each other and disposed at an opposite side of the second memory cell layers with respect to the first gate lines;
second connective lines disposed in contact with the second gate lines at opposite sides of the second gate lines along the second direction;
and
second landing pads disposed in contact with the second connective lines along the second direction and as wide as the first landing pads along the first direction,
wherein the second connective lines are shorter than the first connective lines along the second direction,
the first landing pads are disposed at different level heights along the second direction than the second landing pads, and
the stacking direction, the first direction, and the second direction are orthogonal directions.

12 more elements

A manufacturing method of a semiconductor device, comprising:

alternately stacking dielectric layers and conductive layers in a multi-layer stack over a semiconductor substrate;
and
sequentially patterning the multi-layer stack to form a multi-layered structure having a central region and a pair of staircases comprising flights of steps extending along a first direction at opposite sides of the central region, wherein top surfaces of the conductive layers are exposed in correspondence of the steps, the flights of steps comprise connective lines and landing pads alternately disposed along the first direction, the connective lines are narrower than the landing pads along a second direction perpendicular to the first direction, and, for adjacent flights of steps, the landing pads of a flight of steps are disposed along the second direction in between connective lines of the adjacent flights of steps.

Dependencies are inferred from the claim text.

Memory cell array, semiconductor device including the same, and manufacturing method thereof

Life of this patent

Memory cell array, semiconductor device including the same, and manufacturing method thereof

Life of this patent

Abstract

Claims20