Semiconductor Package and Method of Manufacture

A semiconductor device comprising:

• an integrated circuit die coupled to an interconnect structure, the interconnect structure comprising:
• one or more metallization patterns disposed in one or more dielectric layers;
• a top dielectric layer over the one or more metallization patterns and the one or more dielectric layers;
• and
• a top metallization pattern electrically coupled to the one or more metallization patterns, wherein the top metallization pattern comprises a via portion extending through the top dielectric layer, wherein a top surface of the via portion is level with a top surface of the top dielectric layer;
• an under-bump metallization extending along the top surface of the top dielectric layer and the top surface of the via portion of the top metallization pattern, wherein a first distance is measured between an edge of the under-bump metallization closest to a centerline of the integrated circuit die and an edge of the via portion closest to the centerline of the integrated circuit die, wherein a second distance is measured between an edge of the under-bump metallization furthest from the centerline of the integrated circuit die and an edge of the via portion furthest from the centerline of the integrated circuit die, and wherein a first difference between the first distance and the second distance is positive;
• and
• a conductive contact coupled to the under-bump metallization.

A method comprising:

• forming an interconnect structure over a first carrier;
• bonding a first die to the interconnect structure;
• removing the first carrier from the interconnect structure, wherein a first via portion of a first metallization pattern of the interconnect structure opposite the first die is exposed after removing the first carrier;
• and
• forming a first UBM over and in physical contact with the first via portion, wherein a centerline of the first UBM is offset from a centerline of the first via portion.