Electronic package structure and fabrication method thereof
AssigneeRichWave Technology Corp.
InventorYu-Lung Wen
Life of this patent
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Abstract
An electronic package structure includes: a substrate having an upper surface; a solder mask layer disposed on the upper surface of the substrate, at least one outer side of the solder mask layer being aligned with at least one outer side of the substrate; an electronic component with a first surface provided on the upper surface of the substrate; and a cavity located between the electronic component and the solder mask layer. A first surface of the cavity is formed by the first surface of the electronic component.
Claims20
An electronic package structure, comprising:
- a substrate having an upper surface;
- a solder mask layer, disposed on the upper surface of the substrate, wherein at least one outer side of the solder mask layer is aligned with at least one outer side of the substrate;
- an electronic component, disposed on the upper surface of the substrate, wherein the electronic component has a first surface;
- and
- a cavity, located between the electronic component and the solder mask layer, wherein a first surface of the cavity is formed by the first surface of the electronic component.
A method of manufacturing an electronic package structure, comprising:
- providing a substrate, wherein the substrate has an upper surface;
- forming a solder mask layer on the upper surface of the substrate;
- forming a recessed area in the solder mask layer;
- mounting an electronic component on the substrate, wherein the electronic component has a first surface, the upper surface of the substrate has a plurality of pads, the first surface of the electronic component has a plurality of bumps, and wherein the plurality of pads respectively corresponds to the plurality of bumps, and the plurality of pads are electrically connected to the plurality of bumps;
- and
- performing a heat treatment, to make the first surface close to the substrate and form a cavity in the recessed area, wherein the cavity is between the first surface of the electronic component, the solder mask layer and the upper surface of the substrate.
Dependencies are inferred from the claim text.