Device for detecting margin of circuit operating at certain speed

A device for detecting a margin of a circuit operating at a circuit operating speed, the device comprising:

• a signal generating circuit configured to generate an input signal including predetermined data at a beginning of a detection process;
• an adjustable delay circuit coupled to the signal generating circuit, and configured to delay the input signal by a first delay amount to generate a delayed input signal;
• a circuit under test (CUT) coupled to the adjustable delay circuit, and configured to perform a predetermined operation after the beginning of the detection process to generate a to-be-tested signal according to the delayed input signal, wherein the predetermined operation is based on a predetermined operation timing;
• a comparison circuit coupled to the CUT, and configured to compare data included in the to-be-tested signal with the predetermined data according to the predetermined operation timing in the detection process and thereby generate a comparison result;
• and
• a calibration circuit coupled to the comparison circuit, and configured to determine whether the CUT passes a speed test according to the comparison result in the detection process.

A device for detecting a margin of a circuit operating at a circuit operating speed, the device comprising:

• a signal generating circuit configured to generate an input signal including predetermined data at a beginning of a detection process;
• a circuit under test (CUT) coupled to the signal generating circuit, and configured to perform a predetermined operation after the beginning of the detection process to generate a to-be-tested signal according to the input signal, wherein the predetermined operation is based on a predetermined operation timing;
• an adjustable delay circuit coupled to the CUT, and configured to delay the to-be-tested signal by a second delay amount to generate a delayed to-be-tested signal;
• a comparison circuit coupled to the adjustable delay circuit, and configured to compare data included in the delayed to-be-tested signal with the predetermined data according to the predetermined operation timing in the detection process and thereby generate a comparison result;
• and
• a calibration circuit coupled to the comparison circuit, and configured to determine whether the CUT passes a speed test according to the comparison result in the detection process.