US 2022/0036955 A1 · HIGH-SPEED EFFICIENT LEVEL SHIFTER

Abstract

Embodiments disclosed herein relate to level shifters of a memory device. Specifically, the level shifters include a first series arrangement of transistors to offset a first transistor. The level shifters also include a second series arrangement of transistors to offset a second transistor. The first series arrangement is opposite the second series arrangement. The output of the first series arrangement is coupled to a first pull-up transistor and configured to cut off a pull-up of the first pull-up transistor to a first voltage. The output of the second series arrangement is coupled to a second pull-up transistor and configured to cut off a pull-up of the second pull-up transistor to the first voltage. The first series arrangement and the second series arrangement are coupled to a second voltage at different times. The series arrangements of transistors enable faster level shifting over conventional level shifters.

Claims20

Dependent claims

A voltage level shifter, comprising:

an input configured to receive a data signal;
a first node configured to provide an output for the voltage level shifter;
a first transistor coupled to the first node and configured to selectively couple the first node to a first voltage level based on the data signal;
a first series arrangement of a second transistor and a third transistor coupled to a second voltage level and configured to selectively couple a second node to the second voltage level;
and
a fourth transistor coupled to the second node and configured to selectively couple the second node to a third voltage level when the second transistor and the third transistor are both activated.

3 more elements

Dependencies are inferred from the claim text.

High-speed efficient level shifter

Life of this patent

High-speed efficient level shifter

Life of this patent

Abstract

Claims20