Memory device and operation method thereof

A memory device comprising:

• a first transistor configured to receive a system power supply voltage;
• a second transistor configured to receive a system ground voltage;
• a memory array, coupled to the first transistor and the second transistor, comprising static random access memory cells, wherein the static random access memory cell has a first local power supply assist voltage node, a second local power supply assist voltage node, a third local power supply assist voltage node, a first local source assist voltage node, a second local source assist voltage node, a third local source assist voltage node, a fourth local source assist voltage node, a first local word-line assist voltage node, and a second local word-line assist voltage node, wherein the first local power supply assist voltage node, the second local power supply assist voltage node, and the third local power supply assist voltage node are configured to receive the system power supply voltage, a first power supply assist voltage, or a second power supply assist voltage, and the first power supply assist voltage and the second power supply assist voltage are substantially less than the system power supply voltage and higher than the system ground voltage;
• wherein the first local source assist voltage node, the second local source assist voltage node, the third local source assist voltage node, the fourth local source assist voltage node are configured to receive the system ground voltage, a first source assist voltage, or a second source assist voltage, and the first source assist voltage and the second source assist voltage are substantially higher than the system ground voltage and less than the system power supply voltage;
• wherein the first local word-line assist voltage node and the second local word-line assist voltage node are configured to receive the system ground voltage, a first word-line assist voltage, or a second word-line assist voltage, the first word-line assist voltage is substantially equal to the system power supply voltage, and the second word-line assist voltage is substantially higher than the system ground voltage and less than the system power supply voltage;
• a power-supply assist-voltage generator circuit coupled to the first local power supply assist voltage node, the second local power supply assist voltage node, and the third local power supply assist voltage node, wherein the power-supply assist-voltage generator circuit is configured to receive a standby control signal and a write-mode or deep sleep control signal, and the power-supply assist-voltage generator circuit is configured to generate the second power supply assist voltage at the first local power supply assist voltage node, the second local power supply assist voltage node, and the third local power supply assist voltage node in response to the write-mode or deep sleep control signal in a write mode or deep sleep mode, the power-supply assist-voltage generator circuit is configured to generate the system power supply voltage at the first local power supply assist voltage node in a read mode or a hold mode, and the power-supply assist-voltage generator circuit is configured to generate the system power supply voltage at the second local power supply assist voltage node and the third local power supply assist voltage node in response to the standby control signal and the write-mode or deep sleep control signal in a read mode or a hold mode;
• a source assist-voltage generator circuit coupled to the first local source assist voltage node, the second local source assist voltage node, the third local source assist voltage node, and the fourth local source assist voltage node, wherein the source assist-voltage generator circuit is configured to receive the standby control signal, a first hold-mode control signal, and a second hold-mode control signal, the source assist-voltage generator circuit is configured to generate the first source assist voltage at the first local source assist voltage node, the second local source assist voltage node, the third local source assist voltage node, and the fourth local source assist voltage node in response to the standby control signal in a standby mode, the source assist-voltage generator circuit is configured to generate the second source assist voltage at the first local source assist voltage node and the third local source assist voltage node in response to the first hold-mode control signal in a hold mode, the source assist-voltage generator circuit is configured to generate the second source assist voltage at the second local source assist voltage node and the fourth local source assist voltage node in response to the second hold-mode control signal in a hold mode, the source assist-voltage generator circuit is configured to generate the system ground voltage at the first local source assist voltage node and the second local source assist voltage node in a read or write mode, the source assist-voltage generator circuit is configured to generate the system ground voltage at the third local source assist voltage node in response to the standby control signal and the first hold-mode control signal in a read or write mode, and the source assist-voltage generator circuit is configured to generate the system ground voltage at the fourth local source assist voltage node in response to the standby control signal and the second hold-mode control signal in a read or write mode;
• and
• a word-line assist-voltage generator circuit coupled to the first local word-line assist voltage node and the second local word-line assist voltage node, wherein the word-line assist-voltage generator circuit is configured to receive a word-line underdrive control signal, a first decoded word-line signal, and a second decoded word-line signal, the word-line assist-voltage generator circuit is configured to generate the first word-line assist voltage at the second local word-line assist voltage node in response to the word-line underdrive control signal or generate the second word-line assist voltage at the second local word-line assist voltage node in response to the second decoded word-line signal in a write mode, the word-line assist-voltage generator circuit is configured to generate the system ground voltage at the first local word-line assist voltage node in response to the word-line underdrive control signal and the first decoded word-line signal in a hold mode or a standby mode, and the word-line assist-voltage generator circuit is configured to generate the system ground voltage at the second local word-line assist voltage node in response to the word-line underdrive control signal and the second decoded word-line signal in a hold mode or a standby mode.