Memory Power-Gating Techniques

A level shifter comprising:

• data control circuitry that provides activation signals in the first voltage domain;
• logic circuitry that provides an output signal in a second voltage domain based on the activation signals in the first domain;
• and
• latch circuitry that provides a latched control signal to a power-gate of the logic circuitry based on the activation signals so as to trigger activation of the logic circuitry to thereby provide the output signal in the second voltage domain.

A voltage tracker comprising:

• first inversion logic coupled between a core voltage and ground, wherein the first inversion logic is configured to provide a first control signal based on an input signal;
• second inversion logic coupled between the input signal and ground, wherein the second inversion logic is configured to receive the first control signal and provide a second control signal when activated by the first control signal;
• and
• power-gate logic coupled between a periphery voltage and the first inversion logic, wherein the power-gate logic is activated by the second control signal to thereby provide the periphery voltage to the first inversion logic,
• wherein the first inversion logic and the power-gate logic are coupled together to operate as a voltage level detector.