Frame buffer compressing circuitry and image processing apparatus

Frame buffer compressing circuitry comprising:

• encoder circuitry configured to receive source data and generates compressed data;
• and
• decoder circuitry configured to decompress the compressed data and outputs the output data,
• wherein the encoder circuitry is configured to perform compression in a lossy mode when an accumulated compressibility of the compressed data exceeds a reference compressibility, and otherwise, the encoder circuitry is configured to perform compression in a lossless mode, and
• wherein the decoder circuitry is configured to perform decompression according to a compression mode corresponding to the compressed data.

An image processing apparatus comprising:

• a memory configured to store compressed data;
• and
• a frame buffer compressing circuitry which includes encoder circuitry configured to compress at least some of source data to generate the compressed data and transmit the compressed data to the memory, and decoder circuitry configured to read and decompress the compressed data from the memory,
• wherein the compressed data includes a payload and a header including actual compressed data and flag,
• wherein the frame buffer compressing circuitry is configured to reflect a result obtained by comparing an accumulated compressibility corresponding to the compressed data with a reference compressibility in the flag, and is configured to perform compression or decompression in a lossy mode or a lossless mode depending on the flag.