Circuit for driving gate, display module, and display device

A display module, comprising:

• a display panel;
• and
• a circuit for gate driving, wherein the circuit comprises N row-driving circuits arranged in cascade and auxiliary circuits arranged corresponding to each row-driving circuit, the N row-driving circuits and N auxiliary circuits are arranged at opposite sides of the display panel, wherein:
• each row-driving circuit comprises a signal input end, a pull-up control signal end and an output end for gate driving signal;
• an Nth row-driving circuit is configured to output an Nth gate driving signal in response that the signal input end receives an (N−1)th gate driving signal output from the (N−1)th row-driving circuit, and to control an Nth sub pixel to charge;
• each auxiliary circuit is arranged corresponding to one row-driving circuit on the array substrate, and each auxiliary circuit comprises an input end, a controlled end and an output end,
• an Nth auxiliary circuit is for receiving the (N−1)th gate driving signal at the input end, the controlled end of the Nth auxiliary circuit is connected with the pull-up control signal end of the Nth row-driving circuit, and the output end of the Nth auxiliary circuit is connected with the output end for gate driving signal of the Nth row-driving circuit;
• the Nth auxiliary circuit is configured to control the sub pixels at the Nth row to charge, in response that both the (N−1)th gate driving signal from the input end and the (N−1)th pull-up control signal from the controlled end are at high level, wherein N≥2.

A display device, comprising a circuit for gate driving, wherein the circuit comprises:

• N row-driving circuits arranged in cascade on an array substrate, wherein each row-driving circuit comprises a signal input end, a pull-up control signal end and an output end for gate driving signal;
• an Nth row-driving circuit is configured to output an Nth gate driving signal in response that the signal input end receives an (N−1)th gate driving signal output from the (N−1)th row-driving circuit, and to control an Nth sub pixel to charge;
• N auxiliary circuits, wherein each auxiliary circuit is arranged corresponding to one row-driving circuit on the array substrate, and each auxiliary circuit comprises an input end, a controlled end and an output end, wherein
• an Nth auxiliary circuit is for receiving the (N−1)th gate driving signal at the input end, the controlled end of the Nth auxiliary circuit is connected with the pull-up control signal end of the Nth row-driving circuit, and the output end of the Nth auxiliary circuit is connected with the output end for gate driving signal of the Nth row-driving circuit,
• the Nth auxiliary circuit is configured to control the sub pixels at the Nth row to charge, in response that both the (N−1)th gate driving signal from the input end and the (N−1)th pull-up control signal from the controlled end are at high level, wherein N≥2.