Scan driver and display device

A scan driver comprising a plurality of stages, each stage comprising:

• at least one clock line configured to receive a first clock signal and a second clock signal having different phases;
• a first transistor including a gate receiving an input signal or the second clock signal, a first terminal receiving the input signal, and a second terminal coupled to a shared control node;
• a second transistor including a gate receiving a gate-on voltage, a first terminal coupled to the shared control node, and a second terminal coupled to a first control node;
• a third transistor including a gate coupled to the first control node, a first terminal receiving the first clock signal, and a second terminal coupled to a first output node at which a first scan signal is output;
• a first capacitor including a first electrode coupled to the first control node, and a second electrode coupled to the first output node;
• a fourth transistor including a gate coupled to a shared inverted control node, a first terminal coupled to the first output node, and a second terminal receiving a gate-off voltage;
• a fifth transistor including a gate receiving the first clock signal, a first terminal coupled to the shared control node, and a second terminal coupled to a second control node;
• a sixth transistor including a gate coupled to the second control node, a first terminal receiving the second clock signal, and a second terminal coupled to a second output node at which a second scan signal is output;
• a second capacitor including a first electrode coupled to the second control node, and a second electrode coupled to the second output node;
• and
• a seventh transistor including a gate coupled to the shared inverted control node, a first terminal coupled to the second output node, and a second terminal receiving the gate-off voltage.

A display device comprising:

• a display panel including a plurality of pixels;
• a data driver configured to provide data signals to the plurality of pixels;
• a scan driver configured to provide scan signals to the plurality of pixels, and including a plurality of stages;
• and
• a controller configured to control the data driver and the scan driver,
• wherein each of the plurality of stages includes:
• at least one clock line configured to receive a first clock signal and a second clock signal having different phases;
• a shared input circuit configured to transfer an input signal to a shared control node;
• a first output circuit coupled to the shared control node, configured to transfer a voltage of the shared control node to a first control node, and configured to output a first scan signal of the scan signals in response to a voltage of the first control node and the first clock signal;
• and
• a second output circuit coupled to the shared control node, configured to transfer the voltage of the shared control node to a second control node, and configured to output a second scan signal of the scan signals in response to a voltage of the second control node and the second clock signal.