Gate driving circuit and control method therefor, and display device

A gate driving circuit, comprising:

• a first switching transistor, wherein a first electrode of the first switching transistor is electrically connected to a second node, a second electrode of the first switching transistor is electrically connected to a first voltage terminal for providing a first level, and a gate of the first switching transistor is configured to receive a first input signal;
• a second switching transistor, wherein a first electrode of the second switching transistor is electrically connected to a fourth node, a second electrode of the second switching transistor is electrically connected to the first voltage terminal, and a gate of the second switching transistor is configured to receive the first input signal;
• a third switching transistor, wherein a first electrode of the third switching transistor is electrically connected to a second voltage terminal, a second electrode of the third switching transistor is electrically connected to the second node, and a gate of the third switching transistor is electrically connected to a third node;
• a fourth switching transistor, wherein a first electrode and a gate of the fourth switching transistor are electrically connected to the second voltage terminal, and a second electrode of the fourth switching transistor is electrically connected to the third node;
• a fifth switching transistor, wherein a first electrode of the fifth switching transistor is electrically connected to the second node, a second electrode of the fifth switching transistor is electrically connected to the first voltage terminal, and a gate of the fifth switching transistor is electrically connected to a first node;
• a sixth switching transistor, wherein a first electrode of the sixth switching transistor is electrically connected to the third node, a second electrode of the sixth switching transistor is electrically connected to the first voltage terminal, and a gate of the sixth switching transistor is electrically connected to the first node;
• a seventh switching transistor, wherein a first electrode of the seventh switching transistor is electrically connected to the first node, a second electrode of the seventh switching transistor is electrically connected to the first voltage terminal, and a gate of the seventh switching transistor is electrically connected to the second node;
• an eighth switching transistor, wherein a first electrode of the eighth switching transistor is electrically connected to an output terminal, a second electrode of the eighth switching transistor is electrically connected to the first voltage terminal, and a gate of the eighth switching transistor is electrically connected to the second node;
• a ninth switching transistor, wherein a first electrode of the ninth switching transistor is electrically connected to a third voltage terminal, a second electrode of the ninth switching transistor is electrically connected to the fourth node, and a gate of the ninth switching transistor is electrically connected to a fifth node;
• a tenth switching transistor, wherein a first electrode and a gate of the tenth switching transistor are electrically connected to the third voltage terminal, and a second electrode of the tenth switching transistor is electrically connected to the fifth node;
• an eleventh switching transistor, wherein a first electrode of the eleventh switching transistor is electrically connected to the fourth node, a second electrode of the eleventh switching transistor is electrically connected to the first voltage terminal, and a gate of the eleventh switching transistor is electrically connected to the first node;
• a twelfth switching transistor, wherein a first electrode of the twelfth switching transistor is electrically connected to the fifth node, a second electrode of the twelfth switching transistor is electrically connected to the first voltage terminal, and a gate of the twelfth switching transistor is electrically connected to the first node;
• a thirteenth switching transistor, wherein a first electrode of the thirteenth switching transistor is electrically connected to the first node, a second electrode of the thirteenth switching transistor is electrically connected to the first voltage terminal, and a gate of the thirteen switching transistor is electrically connected to the fourth node;
• a fourteenth switching transistor, wherein a first electrode of the fourteenth switching transistor is electrically connected to the output terminal, a second electrode of the fourteenth switching transistor is electrically connected to the first voltage terminal, and a gate of the fourteenth switching transistor is electrically connected to the fourth node;
• a fifteenth switching transistor, wherein a first electrode of the fifteenth switching transistor is electrically connected to the first node, a second electrode of the fifteenth switching transistor is electrically connected to the first voltage terminal, and a gate of the fifteenth switching transistor is configured to receive a first reset signal;
• a sixteenth switching transistor, wherein a first electrode of the sixteenth switching transistor is electrically connected to the output terminal, a second electrode of the sixteenth switching transistor is electrically connected to the first voltage terminal, and a gate of the sixteenth switching transistor is configured to receive a second reset signal;
• a seventeenth switching transistor, wherein a first electrode of the seventeenth switching transistor is electrically connected to the first node, a second electrode of the seventeenth switching transistor is electrically connected to the first voltage terminal, and a gate of the seventeen switching transistor is configured to receive a global reset signal;
• an eighteenth switching transistor, wherein a first electrode and a gate of the eighteenth switching transistor are configured to receive the first input signal, and a second electrode of the eighteenth switching transistor is electrically connected to the first node;
• a nineteenth switching transistor, wherein a first electrode of the nineteenth switching transistor is configured to receive a second input signal, a second electrode of the nineteenth switching transistor is used as the output terminal, and a gate of the nineteenth switching transistor is electrically connected to the first node;
• and
• a capacitor, wherein a first terminal of the capacitor is electrically connected to the first node, and a second terminal of the capacitor is electrically connected to the second electrode of the nineteenth switching transistor.

A control method for a gate driving circuit, comprising:

• changing a potential of a first node from a first level to a second level by an input sub-circuit under control of a first input signal;
• outputting a gate driving signal in response to a second input signal by an output sub-circuit;
• resetting a potential of an output terminal of the output sub-circuit by a second reset sub-circuit under control of a second reset signal;
• and
• resetting the potential of the first node by a first reset sub-circuit under control of a first reset signal, and maintaining the potential of the first node and the potential of the output terminal of the output sub-circuit at the first level by at least one noise reduction sub-circuit;
• wherein in the changing of the potential of the first node from the first level to the second level by the input sub-circuit, a function maintaining sub-circuit controls operation of the at least one noise reduction sub-circuit under control of the first input signal, so that the at least one noise reduction sub-circuit interrupts electrical coupling between the first node and a first voltage terminal.