Shift register unit and method for driving the same, gate drive circuit and display device

A shift register unit, comprising a first input transistor, a second input transistor, a first output transistor, a second output transistor, a first switching transistor, a second switching transistor, a first capacitor, a second capacitor and a third capacitor,

• a first electrode of the first input transistor is coupled to a first voltage terminal, a second electrode of the first input transistor is coupled to a first node, a gate electrode of the first input transistor is coupled to a first clock signal terminal,
• a first electrode of the second input transistor is coupled to an input terminal of the shift register unit, a second electrode of the second input transistor is coupled to a second node, a gate electrode of the second input transistor is coupled to the first clock signal terminal,
• a first electrode of the first output transistor and one terminal of the third capacitor are both coupled to a second voltage terminal, a second electrode of the first output transistor is coupled to an output terminal of the shift register unit, a gate electrode of the first output transistor and another terminal of the third capacitor are both coupled to the first node,
• a first electrode of the second output transistor and one terminal of the second capacitor are both coupled to a second clock signal terminal, a second electrode of the second output transistor is coupled to the output terminal of the shift register unit, a gate electrode of the second output transistor and another terminal of the second capacitor are both coupled to the second node,
• a first electrode of the first switching transistor is coupled to the first clock signal terminal, a second electrode of the first switching transistor is coupled to the first node, a gate electrode of the first switching transistor is coupled to the second node,
• a first electrode of the second switching transistor is coupled to a third clock signal terminal, a second electrode of the second switching transistor is coupled to a first terminal of the first capacitor, a gate electrode of the second switching transistor is coupled to the first node, a second terminal of the first capacitor is coupled to the second node,
• the first clock signal terminal and the third clock signal terminal are shared.