Circuit, method of driving panel, and display device

A method of driving a panel, applied to a circuit, wherein the circuit comprise:

• a plurality of scanning lines;
• a plurality of clock signal connecting lines;
• a time controller connected with ends of the clock signal connecting lines, and
• multiple shift register units arranged in cascade, wherein input ends of the shift register units are correspondingly connected to other ends of the clock signal connecting lines to receive clock signals sent by the time controller, and output ends of the shift register units are connected with the scanning lines in one-to-one correspondence,
• wherein, starting from a first shift register unit, two adjacent shift register units are taken as a shift register group, and waveforms of the clock signals sent by the time controller to the two adjacent shift register units in a same shift register group are equal via the clock signal connecting lines;
• and
• the method comprises:
• controlling a time controller connected with a plurality of clock signal connecting lines to provide clock signals to multiple shift register units arranged in cascade via the clock signal connecting lines, wherein output ends of the shift register units are connected with a plurality of scanning lines in one-to-one correspondence, starting from a first shift register unit, two adjacent shift register units are taken as a shift register group, and waveforms of the clock signals received by the two adjacent shift register units in a same shift register group are identical;
• and
• controlling the shift register units to convert the clock signals into output signals and transmit the output signals to the scanning lines.

A display device, comprising an array substrate, an opposite substrate arranged opposite to the array substrate, and a liquid crystal cell layer arranged between the array substrate and the opposite substrate,

• wherein the array substrate comprises a circuit comprising:
• a plurality of scanning lines;
• a plurality of clock signal connecting lines;
• a time controller connected with ends of the clock signal connecting lines, and
• multiple shift register units arranged in cascade, wherein input ends of the shift register units are correspondingly connected to other ends of the clock signal connecting lines to receive clock signals sent by the time controller, and output ends of the shift register units are connected with the scanning lines in one-to-one correspondence,
• wherein, starting from a first shift register unit, two adjacent shift register units are taken as a shift register group, and waveforms of the clock signals sent by the time controller to the two adjacent shift register units in a same shift register group are equal via the clock signal connecting lines.