Ray Intersect Circuitry with Parallel Ray Testing
AssigneeApple Inc.
InventorsAli Rabbani Rankouhi, Christopher A. Burns, Justin A. Hensley, Luca Iuliano, Jonathan M. Redshaw
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AssigneeApple Inc.
InventorsAli Rabbani Rankouhi, Christopher A. Burns, Justin A. Hensley, Luca Iuliano, Jonathan M. Redshaw
Estimating the term…
Disclosed techniques relate to ray intersection processing for ray tracing. In some embodiments, ray intersection circuitry traverses a spatially organized acceleration data structure and includes bounding region circuitry configured to test, in parallel, whether a ray intersects multiple different bounding regions indicated by a node of the data structure. Shader circuitry may execute a ray intersect instruction to invoke traversal by the ray intersect circuitry and the traversal may generate intersection results. The shader circuitry may shade intersected primitives based on the intersection results. Disclosed techniques that share processing between intersection circuitry and shader processors may improve performance, reduce power consumption, or both, relative to traditional techniques.
An apparatus, comprising:
A method, comprising:
A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit includes:
Dependencies are inferred from the claim text.