Apparatus with accelerated machine learning processing
AssigneeSamsung Electronics Co., Ltd.
InventorsSaptarsi Das, Sabitha Kusuma, Arnab Roy, Ankur Deshwal, Kiran Kolar Chandrasekharan, Sehwan Lee
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AssigneeSamsung Electronics Co., Ltd.
InventorsSaptarsi Das, Sabitha Kusuma, Arnab Roy, Ankur Deshwal, Kiran Kolar Chandrasekharan, Sehwan Lee
Estimating the term…
An apparatus includes a global memory and a systolic array. The global memory is configured to store and provide an input feature map (IFM) vector stream from an IFM tensor and a kernel vector stream from a kernel tensor. The systolic array is configured to receive the IFM vector stream and the kernel vector stream from the global memory. The systolic array is on-chip together with the global memory. The systolic array includes a plurality of processing elements (PEs) each having a plurality of vector units, each of the plurality of vector units being configured to perform a dot-product operation on at least one IFM vector of the IFM vector stream and at least one kernel vector of the kernel vector stream per unit clock cycle to generate a plurality of output feature maps (OFMs).
An apparatus, the apparatus comprising:
An apparatus, the apparatus comprising:
Dependencies are inferred from the claim text.