Method and apparatus with deep learning operations

A device, comprising:

• an array of a plurality of processing elements,
• wherein the plurality of processing elements include any one or any combination of:
• a first processing element of the array, the first processing element comprising a first multiplexer configured to determine one of an output of an accumulator of the first processing element or an output of a neighboring processing element to be an input of an adder of the first processing element;
• a second processing element of the array, the second processing element comprising a second multiplexer configured to determine one of a predetermined value or an output of a multiplier of the second processing element to be an input of an adder of the second processing element;
• and
• a third processing element comprising a third multiplexer configured to determine one of an output of an adder of the third processing element or a sum of the output of the adder of the third processing element and outputs of neighboring processing elements to be an input of an accumulator of the third processing element.

A deep learning method, the method comprising:

• receiving input data;
• receiving an indication of an operation mode;
• and
• controlling operations of a plurality of multiplier accumulator (MAC) units, arranged in a systolic array, and data movements among the plurality of MAC units in response to the indicated operation mode.

A deep learning apparatus, the apparatus comprising:

• a processor, configured to support a plurality of different operation modes, comprising:
• a systolic array comprising a plurality of multiplier accumulator (MAC) units arranged in two dimensions of rows and columns, and configurable respective row input and/or output data communication paths among multiple MAC units for each of a plurality of the rows, and configurable respective column input and/or output data communication paths among multiple MAC units for each of a plurality of the columns;
• and
• a control circuitry, for the systolic array, configured to respectively reconfigure the systolic array to respectively operate differently in at least two of an adder tree mode, a single instruction multiple data (SIMD) mode, a systolic adder tree mode, and a systolic mode for input data.