Memory cell array circuit and method of forming the same

A memory cell array comprising:

• a first column of memory cells;
• a second column of memory cells being separated from the first column of memory cells in a first direction, the first column of memory cells and the second column of memory cells being arranged in a second direction different from the first direction;
• a first bit line coupled to the first column of memory cells, and extending in the second direction;
• a second bit line coupled to the second column of memory cells, and extending in the second direction, the first bit line or the second bit line comprises:
• a first conductive line extending in the second direction, and being located on a first metal layer;
• and
• a second conductive line extending in the second direction, and being located on a second metal layer above the first metal layer, the first conductive line and the second conductive line overlap a source of a transistor of a memory cell of the first column of memory cells or the second column of memory cells;
• a source line extending in the second direction, being coupled to the first column of memory cells and the second column of memory cells;
• and
• a first set of vias electrically coupled to the first conductive line and the second conductive line, and being between the first conductive line and the second conductive line, a pair of vias of the first set of vias being located above where the first conductive line overlaps each memory cell of the first column of memory cells or the second column of memory cells.

A method of forming a memory cell array, the method comprising:

• generating, by a processor, a layout design of the memory cell array, wherein the generating of the layout design comprises:
• placing a first set of memory cell layout patterns in a first column, the first set of memory cell layout patterns corresponding to fabricating a first set of memory cells, each layout pattern of the first set of memory cell layout patterns being separated from an adjacent layout pattern of the first set of memory cell layout patterns in a first direction;
• placing a second set of memory cell layout patterns in a second column separated from the first column in a second direction different from the first direction, the second set of memory cell layout patterns corresponding to fabricating a second set of memory cells, each layout pattern of the second set of memory cell layout patterns being separated from an adjacent layout pattern of the second set of memory cell layout patterns in the first direction;
• placing a first set of conductive feature layout patterns in the first column, the first set of conductive feature layout patterns extending in the first direction and overlapping the first set of memory cell layout patterns, the first set of conductive feature layout patterns corresponding to fabricating a first bit line extending in the first direction and being coupled to the first set of memory cells;
• and
• placing a second set of conductive feature layout patterns in the second column, the second set of conductive feature layout patterns extending in the first direction and overlapping the second set of memory cell layout patterns, the second set of conductive feature layout patterns corresponding to fabricating a second bit line extending in the first direction and being coupled to the second set of memory cells;
• and
• manufacturing the memory cell array based on the layout design.