Deadlock condition avoidance in a data processing system with a shared slave

A processing system comprising:

• bus master devices;
• bus slave devices;
• arbitration circuitry coupled between the bus master devices and the bus slave devices;
• a master access queue for each of the bus slave devices, each entry of the master access queue indicating whether a first of the bus master devices is accessing a respective one of the bus slave devices while a second of the bus master devices is waiting to access the one of the bus slave devices;
• counter circuits corresponding to each of the bus slave devices, the counter circuits configured to reset to a starting value upon expiration of a specified time period;
• a deadlock condition detection control circuit configured to assert a deadlock condition indicator when the first of the bus master devices is accessing the one of the bus slave devices when one of the counters corresponding to the one of the bus slave devices is reset and an entry in one of the master access queues corresponding to the one of the bus slave devices indicates the second of the bus master devices is waiting to access the one of the bus slave devices.

A method of controlling deadlock in a processing system comprising:

• asserting a deadlock condition indicator when:
• a timer in a timer circuit has passed a predetermined period of time while a first bus master device occupies a port of a bus slave device, and
• an empty indicator indicates a second bus master is waiting to occupy the port of the bus slave device while the first bus master is occupying the port of the bus slave device;
• and
• taking an action to eliminate the deadlock when the deadlock condition indicator is asserted.