Signaling mechanism for bus inversion

An apparatus, comprising:

• a controller that is configured to cause the apparatus to:
• transmit a command to a memory device over a bus that is coupled with the controller and the memory device;
• pulse a voltage of a control pin that is coupled with the controller and the memory device to enable reception of the command at the memory device;
• invert, based at least in part on a content of a set of data associated with the command, the set of data to obtain an inverted set of data;
• set, after the voltage of the control pin is pulsed, the voltage of the control pin to a level that indicates that corresponding data on the bus is in an inverted state;
• and
• transmit, over the bus, the inverted set of data to the memory device based at least in part on the voltage of the control pin being set to the level.

An apparatus, comprising:

• a memory array;
• a first controller that is coupled with the memory array and configured to cause the apparatus to:
• detect a voltage pulse at a control pin that is coupled with the first controller and a second controller;
• enable, based at least in part on the voltage pulse, a reception of a command over a bus that is coupled with the first controller and the second controller;
• retrieve, from the memory array, a set of data based at least in part on the command;
• and
• set, after the set of data is retrieved, a voltage of the control pin to a level that indicates that corresponding data on the bus is in an inverted state.

An apparatus, comprising:

• a memory array;
• a first controller that is coupled with the memory array and configured to cause the apparatus to:
• detect a voltage pulse at a control pin that is coupled with the first controller and a second controller;
• enable, based at least in part on the voltage pulse, a reception of a command over a bus that is coupled with the first controller and the second controller;
• receive, from the second controller, a set of data associated with the command over the bus based at least in part on the command;
• detect, after the voltage pulse at the control pin is detected, a voltage level of the control pin that indicates that corresponding data on the bus is in an inverted state;
• and
• determine that the set of data is in the inverted state based at least in part on the voltage level of the control pin.