US 2022/0035745 A1 · DATA PROCESSING METHOD AND CHIP, DEVICE, AND STORAGE MEDIUM

Abstract

A data processing method, device, and storage medium that reads a parallel control code; reads, according to the parallel control code, first data that has been cached in a data cache space, processes the read first data, and outputs the processed first data to the data cache space; and simultaneously moves second data from a data storage space to the data cache space according to the parallel control code, the second data being the next data of the first data. Data processing and data moving are performed simultaneously according to the parallel control code, to reduce a duration of the data processing waiting for the data moving, thereby improving a processing speed and processing efficiency.

Claims20

Dependent claims

A data processing method, performed by a computer device, the method comprising:

reading parallel control code;
reading, as instructed by the parallel control code, first data that has been cached in a data cache space, processing the read first data, and outputting processed first data to the data cache space;
and
simultaneously moving second data from a data storage space to the data cache space as instructed by the parallel control code, the second data being next data of the first data.

1 more element

A computer device, comprising:

at least one memory configured to store program code;
at least one data storage;
at least one data cache;
at least one processor configured to access the program code and operate as instructed by the program code, the program code including:
instruction processing code configured to cause the at least one processor to read a parallel control code;
data processing code configured to cause the at least one processor to read, according to the parallel control code, first data that has been cached in the data cache, process the read first data, and output processed first data to the data cache;
and
data moving code configured to cause the at least one processor to simultaneously move second data from the data storage to the data cache according to the parallel control code, the second data being next data of the first data.

5 more elements

A non-volatile computer-readable storage medium, storing computer code that when executed by at least one processor causes the at least one processor to:

read parallel control code;
read, according to the parallel control code, first data that has been cached in a data cache, process the read first data, and output processed first data to the data cache;
and
simultaneously move second data from a data storage to the data cache according to the parallel control code, the second data being next data of the first data.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

17/502,218Filed 15 Oct 2021

Priority

CN 201911235760.X5 Dec 2019

Published

3 Feb 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06F 12/0875
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: with…
G06N 3/063
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons: using electronic means
G06N 3/04
Neural networks: architecture, e.g. interconnection topology
G06N 3/045
Architecture, e.g. interconnection topology: combinations of networks

Data processing method and chip, device, and storage medium

Life of this patent

Data processing method and chip, device, and storage medium

Life of this patent

Abstract

Claims20