System and method for scalable hardware-coherent memory nodes

A multiprocessor system, comprising:

• a first node controller that is directly coupled to a processor;
• and
• a second identical node controller that is not directly coupled to any processor and is coupled to a fabric-attached memory;
• wherein the first node controller is to operate in a first mode to manage cache coherence for a local memory of the processor;
• and
• wherein the second node controller is to operate in a second mode to manage cache coherence for the fabric-attached memory.

A method to manage cache coherence in a multiprocessor system, the method comprising:

• receiving, by a node controller, a memory-access request from a remote node controller in the multiprocessor system;
• in response to determining that a processor is directly coupled to the node controller, configuring the node controller to operate in a first mode such that the node controller manages cache coherence for a local memory of the processor;
• and
• in response to determining that the node controller is not directly coupled to any processor and is coupled to a fabric-attached memory, configuring the node controller to operate in a second mode such that the node controller manages cache coherence for the fabric-attached memory.