Data processing method for controlling write speed of memory device to avoid significant write delay and data storage device utilizing the same
AssigneeSilicon Motion, Inc.
InventorTsung-Yao Chiang
Life of this patent
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AssigneeSilicon Motion, Inc.
InventorTsung-Yao Chiang
Estimating the term…
A memory controller includes a buffer memory and a microprocessor. The buffer memory includes at least a first cache memory and a second cache memory. The microprocessor is configured to control access of a flash memory device. The microprocessor is configured to obtain a number of spare blocks of the flash memory device corresponding to a first operation period, determine a write speed compensation value, determine a target write speed according to the write speed compensation value and a balance speed, and determine a target garbage collection speed according to the target write speed. The microprocessor is further configured to perform one or more write operations in response to one or more write commands received from a host device in the first operation period according to the target write speed and perform at least one garbage collection operation according to the target garbage collection speed.
A memory controller, coupled to a host device and a flash memory device and configured to access the flash memory device, comprising:
A data processing method for a data storage device comprising a memory device and a memory controller, wherein the memory device comprises a plurality of memory blocks and the memory blocks comprising a plurality of spare blocks, and the data processing method comprises:
A data storage device, coupled to a host device, comprising:
Dependencies are inferred from the claim text.