Error correction methods and semiconductor devices and semiconductor systems using the error correction methods and the semiconductor devices

A semiconductor device comprising:

• an error correction circuit configured to detect an error included in first and second internal data, to generate a failure detection signal during a read operation, and to correct the error included in the first and second internal data during a refresh operation;
• a refresh control circuit configured to store an address signal for activating a word line in which the first and second internal data including an error are stored as first and second failure address signals, to output the first and second failure address signals during the refresh operation, and to control a read modify write operation during the refresh operation;
• and
• a core circuit configured to output the first and second internal data stored in the core circuit through the word line activated by the first and second failure address signals during the read modify write operation, and then, store the error-corrected first and second internal data.

A semiconductor device comprising:

• an error correction circuit configured to detect an error included in internal data, to generate a failure detection signal during a read operation, and to correct the error included in the internal data during a refresh operation;
• a core circuit configured to store an address signal for activating a word line in which the internal data including the error is stored as a failure address signal when the failure detection signal is input to the core circuit and store the error-corrected internal data in the core circuit through a word line activated by the failure address during the refresh operation;
• and
• a repair control circuit configured to generate a repair signal for replacing the word line in which the internal data is stored through with another word line when the failure address signal is generated with the same logic level combination.

An error correction method comprising:

• performing an address detection operation to detect an error included in internal data output from a memory region during a read operation;
• performing an error correction operation to generate a failure detection signal when an error is included in the internal data and to correct the error of the internal data;
• and
• performing an address storage operation to store an address signal for activating a word line in which the internal data is stored through as a failure address signal when the failure detection signal occurs, wherein error-corrected internal data is stored through the word line activated by the failure address signal during a refresh operation.