Memory system including field programmable gate array (fpga) and method of operating same
AssigneeSamsung Electronics Co., Ltd.
InventorsDONG-MIN SHIN, HONG-RAK SON
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Abstract
A memory system includes; a memory device, a memory controller including a first interface, a second interface, and a first data processor having a first error correction code (ECC) engine, and a field programmable gate array (FPGA) including a third interface connected to the first interface, a fourth interface connected to the second interface, a fifth interface connected to an external host, and a second data processor having a second ECC engine. The memory controller may configure a normal write operation path or highly reliable write operation path.
Claims20
A memory system comprising:
- a memory device;
- and
- a memory controller comprising a first interface, a second interface, a first data processor, and a second data processor,
- wherein the first data processor is configured to perform a first data processing on read data retrieved via the first interface from the memory device and output the first processed read data via one of the second interface and the second data processor,
- wherein the second data processor is configured to perform a second data processing on the first processed read data and output the second processed read data to an external host via the second interface, and
- wherein the second data processor comprises a second error correction code (ECC) engine configured to perform a second ECC decoding on the first-processed read data received from the first data processor to provide the second-processed read data.
A memory system comprising:
- a memory device;
- and
- a memory controller comprising a first interface connected to the memory device, a second interface connected to an external host, a first data processor including a first error correction code (ECC) engine and a second data processor including a second ECC engine,
- wherein the memory controller is configured to determine whether a write operation requested from the external host is a normal write operation or a highly reliable write operation,
- upon determining that the write operation is the normal write operation, the memory controller configures a normal write operation path from the external host to the memory device, wherein the normal write operation path includes the second interface, the first data processor, and the first interface, else
- upon determining that the write operation is the highly reliable write operation, the memory controller configures a highly reliable write operation path from the external host to the memory device, wherein the highly reliable write operation path includes the second interface, the second data processor, the first data processor, and the first interface.
A method of operating a memory system comprising a field programmable gate array (FPGA), which is operated based on a program, and a memory device, the method comprising:
- selecting one from a normal path and a highly reliable path to write first data to the memory device;
- in response to selecting the highly reliable path, performing second error correction code (ECC) encoding on the first data, the second ECC encoding generating ECC parity bits varying based on the program;
- performing first ECC encoding on the first data having undergone the second ECC encoding;
- and
- storing the first data having undergone the first ECC encoding in the memory device according to a first writing method.
Dependencies are inferred from the claim text.