Reverse restartable sequences for lock polling scalability

A system comprising:

• a memory;
• at least one processor in communication with the memory;
• a plurality of threads executing on the at least one processor;
• and
• a supervisor configured to:
• preempt a first thread;
• determine a status of the first thread as one of (i) executing in an atomic section and (ii) executing outside of the atomic section, wherein the atomic section is a region of code tagged as atomic;
• and
• responsive to determining the status as executing in the atomic section, notify a second thread to enter a sleep state after polling.

A non-transitory computer readable medium storing instructions, which when executed by a processor, cause the processor to:

• preempt, by a supervisor, a first thread;
• determine, by the supervisor, a status of the first thread as one of (i) executing in an atomic section and (ii) executing outside of the atomic section, wherein the atomic section is a region of code tagged as atomic;
• and
• responsive to determining the status as executing in the atomic section, notify, by the supervisor, a second thread to enter a sleep state after polling.