US 2022/0035644 A1 · DIRECTED INTERRUPT VIRTUALIZATION WITH FALLBACK

Abstract

A processor receives an interrupt signal. The interrupt signal is received with an interrupt target ID identifying a target processor for handling the interrupt signal. The processor is a target of the interrupt signal directly. A check is made as to whether the processor is the target processor identified by the interrupt target ID. The checking includes performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor. Based on the checking being successful, the interrupt signal is accepted for handling by the processor.

Claims20

Dependent claims

A computer program product for facilitating processing within a computing environment, the computer program product comprising:

one or more computer readable storage media and program instructions collectively stored on the one or more computer readable storage media to perform a method comprising:
receiving, by a processor, an interrupt signal, the interrupt signal being received with an interrupt target ID identifying a target processor for handling the interrupt signal, the processor being a target of the interrupt signal directly;
checking whether the processor is the target processor identified by the interrupt target ID, the checking comprising performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor;
and
accepting, based on the checking being successful, the interrupt signal for handling by the processor.

2 more elements

A computer system for facilitating processing within a computing environment, the computer system comprising:

a memory;
and
at least one processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
receiving, by a processor, an interrupt signal, the interrupt signal being received with an interrupt target ID identifying a target processor for handling the interrupt signal, the processor being a target of the interrupt signal directly;
checking whether the processor is the target processor identified by the interrupt target ID, the checking comprising performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor;
and
accepting, based on the checking being successful, the interrupt signal for handling by the processor.

4 more elements

A computer-implemented method of facilitating processing within a computing environment, the computer-implemented method comprising:

receiving, by a processor, an interrupt signal, the interrupt signal being received with an interrupt target ID identifying a target processor for handling the interrupt signal, the processor being a target of the interrupt signal directly;
checking whether the processor is the target processor identified by the interrupt target ID, the checking comprising performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor;
and
accepting, based on the checking being successful, the interrupt signal for handling by the processor.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

17/506,368Filed 20 Oct 2021

Priority

EP EP19157105.814 Feb 2019

Published

3 Feb 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 9/45545
Hypervisors; Virtual machine monitors: guest-host, i.e. hypervisor is an application program itself, e.g. VirtualBox
G06F 9/4812
Task transfer initiation or dispatching: by interrupt, e.g. masked
G06F 9/4881
By program, e.g. task dispatcher, supervisor, operating system: scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
G06F 9/5027
To service a request: the resource being a machine, e.g. CPUs, Servers, Terminals

Directed interrupt virtualization with fallback

Life of this patent

Directed interrupt virtualization with fallback

Life of this patent

Abstract

Claims20