On-the-fly adjustment of issue-write back latency to avoid write back collisions using a result buffer

A system for avoiding a write back collision in a register file, comprising:

• a pipeline queue configured to manage a plurality of instructions processed through at least two pipes;
• a result buffer, separate from the at least two pipes, configured to delay processing of results for at least one of the plurality of instructions;
• and
• a write back port to write back results of the plurality of instructions to the register file, wherein the write back port is configured to receive results from the results buffer and the at least two pipes.

A computer readable storage medium configured for avoiding write back collisions having computer executable instructions that when executed cause a computing system to perform a method of:

• receiving a plurality of instructions at a pipeline queue;
• determining, by an issue queue, a number of cycles for each instruction of the plurality of instructions;
• determining, by the issue queue, if a collision will occur between at least two of the instructions of the plurality of instructions;
• determining, in response to a determined collision between the at least two of the instructions of the plurality of instructions, a number of cycles to delay at least one instruction of the at least two instructions;
• executing the plurality of instructions;
• for the at least one instruction for which a delay was determined, placing results of the at least one instruction in a result buffer for the determined number of cycles of delay;
• after the determined number of cycles of delay, sending the results to a results mux;
• and
• performing a write back process for the at least one instruction.