US 2022/0035635 A1 · PROCESSOR WITH MULTIPLE EXECUTION PIPELINES

Abstract

An apparatus and method system and method for increasing performance in a processor or other instruction execution device while minimizing energy consumption. A processor includes a first execution pipeline and a second execution pipeline. The first execution pipeline includes a first decode unit and a first execution control unit coupled to the first decode unit. The first execution control unit is configured to control execution of all instructions executable by the processor. The second execution pipeline includes a second decode unit, and a second execution control unit coupled to the second decode unit. The second execution control unit is configured to control execution of a subset of the instructions executable via the first execution control unit.

Claims20

Dependent claims

A processing device comprising:

an instruction fetch unit;
a first decode unit coupled to the instruction fetch unit;
a first execution control unit coupled to the first decode unit;
a second decode unit coupled to the instruction fetch unit;
a second execution control unit coupled to the second decode unit;
and
a set of execution units coupled to the first execution control unit and the second execution control unit wherein:
the first decode unit and the first execution control unit are configured to cause the set of execution units to execute any instruction of a first instruction set;
and
the second decode unit and the second execution control unit are configured to cause the set of execution units to execute any instruction of a second instruction set that is a subset of the first instruction set such that a remainder of the first instruction set is not in the second instruction set.

7 more elements

Dependencies are inferred from the claim text.

Processor with multiple execution pipelines

Life of this patent

Processor with multiple execution pipelines

Life of this patent

Abstract

Claims20