Microprocessor that fuses load and compare instructions

A computer-implemented method (CIM) comprising:

• receiving, by an instruction fetch unit of a load-store architecture style processor, a load instruction including an RT field value;
• receiving, by the instruction fetch unit, a compare-immediate instruction including an RA field value;
• determining that the load instruction and the compare-immediate instruction are consecutive instructions;
• determining, by the instruction fetch unit, that an immediate field of the compare-immediate instruction has a value that falls within a predetermined range of values;
• responsive to the determination that the load instruction and the compare-immediate instruction are consecutive instructions and further responsive to the determination that that an immediate field of the compare-immediate instruction has a value that falls within a predetermined range of values, fusing, by the instruction fetch unit, the load instruction and the compare-immediate instruction to form a single fused instruction;
• and
• generating an early compare result to provide a condition code representing an answer to a compare earlier to a dependent branch instruction so that the dependent branch instruction can determine whether a given branch should have been taken.