Wafer sensitivity determination and communication
AssigneeSynopsys, Inc.
InventorThomas CECIL
Life of this patent
Estimating the term…
Abstract
A method comprises receiving an integrated circuit (IC) chip design, and generating, by one or more processors, a wafer image and a wafer target from the IC chip design. The method further comprises generating, by the one or more processors, sensitivity information based on a determination that the wafer image and the wafer target converge, and outputting the sensitivity information. The sensitivity information is associated with writing a mask written for the IC chip design.
Claims20
A method comprising:
- receiving an integrated circuit (IC) chip design;
- generating, by one or more processors, a wafer image and a wafer target from the IC chip design;
- generating, by the one or more processors, sensitivity information based on a determination that the wafer image and the wafer target converge;
- and
- outputting the sensitivity information, wherein the sensitivity information is associated with writing a mask written for the IC chip design.
A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
- receive an integrated circuit (IC) chip design;
- generate a wafer image and a wafer target from the IC chip design;
- generate sensitivity information based on a determination that the wafer image and the wafer target converge;
- and
- output the sensitivity information to a mask writing device.
A lithography system comprising:
- a memory;
- and
- a processor coupled with the memory, the processor configured to:
- receive an integrated circuit (IC) chip design;
- generate a wafer image and a wafer target from the IC chip design;
- generate sensitivity information based on a determination that the wafer image and the wafer target converge;
- and
- output the sensitivity information to a mask writing device.
Dependencies are inferred from the claim text.