Pixel architecture, array substrate and display apparatus

A pixel architecture comprising:

• a plurality of sub-pixels arranged in an array;
• a plurality of gate lines extending in a first direction, the first direction being a row direction in which the plurality of sub-pixels are arranged;
• and two gate lines of the plurality of gate lines being provided between every two adjacent rows of sub-pixels;
• a plurality of data lines, each data line including a plurality of first extension portions and a plurality of second extension portions that are alternately connected, each first extension portion extending in the first direction, each second extension portion extending in a second direction, and the first direction intersecting the second direction;
• wherein
• the plurality of gate lines and the plurality of data lines define a plurality of pixel regions, and two sub-pixels arranged in the first direction are provided in each pixel region;
• in the data line, every two adjacent first extension portions and a second extension portion connected between the two adjacent first extension portions constitute a projection portion accommodating at least one pixel region;
• and
• every two adjacent data lines are configured to transmit data voltage signals with opposite voltage polarities;
• all sub-pixels in each projection portion are coupled to a same data line to receive data voltage signals with same voltage polarity;
• sub-pixels in two adjacent projection portions in the second direction are respectively coupled to two adjacent data lines to receive data voltage signals with opposite voltage polarities.