A Vertical Silicon Carbide Power MOSFET and IGBT and a Method of Manufacturing the Same

A vertical silicon carbide power MOSFET, comprising:

• a drain formed by a 4H-SiC substrate with n+ type doping;
• a drift region comprising a 4H-SiC epilayer with n-type doping, the 4H-SiC epilayer being epitaxially grown on the 4H-SiC substrate;
• a source region with p++ type doping disposed in the drift region;
• a well region with p type doping disposed into the drift region;
• a channel region with p type doping disposed into the drift region;
• a contact region with n++ type doping disposed into the drift region;
• a metal gate insulated from the source region and the drift region by a gate-oxide;
• and
• a high mobility layer comprising a3C-SiC epilayer, the high mobility layer located at an interface between the 4H-SiC epilayer and the gate-oxide and having a vertical thickness between 0.1 nm to 50 nm.

A vertical silicon carbide power Insulated Gate Bipolar Transistor (IGBT), comprising:

• a field stop layer formed by a 4H-SiC substrate with n type doping;
• a drift region comprising a 4H-SiC epilayer of n-type, 4H-SiC epilayer having been epitaxially grown the 4H-SiC substrate;
• an emitter region of p++ type doping disposed in the drift region;
• a well region of p-type doping disposed in the drift region;
• a channel region of p-type doping disposed in the drift region;
• a contact region with n++ type doping disposed in the drift region;
• a metal gate insulated from the emitter region and the drift region by a gate-oxide;
• a collector layer of p+ type doping disposed on a surface of the field stop layer, the field stop layer disposed between the drift region and the collector layer;
• and
• a high mobility layer comprising a 3C-Si epilayer located at an interface between the 4H-SiC epilayer and the gate-oxide, wherein the high mobility layer having a vertical thickness between 0.1 nm to 50 nm.

A method of forming a semiconductor device, the method comprising:

• epitaxially growing a 4H-SiC epilayer on a 4H-SiC substrate, the 4H-SiC epilayer having n type doping and the 4H-SiC substrate having n type doping;
• implanting a first region of p++ type, a second region of p type, a third region of p type and a fourth region of n++ type in a surface of the 4H-SiC epilayer;
• epitaxially growing a 3C-SiC layer on the implanted surface of the 4H-SiC epilayer, wherein the 3C-SiC layer is grown to a vertical thickness of 0.1 to 50 nm;
• partially oxidizing the 3C-SiC layer;
• depositing an insulation layer over the 3C-SiC layer;
• and
• forming a metal region on the insulation layer.