Multichip package manufacturing process

A multichip package manufacturing process for making a multichip package comprising a package carrier board and a plurality of ICs, said package carrier board comprising a die-bonding area and a plurality of external pins provided at at least one side of said die-bonding area, said die-bonding area being provided for the bonding of said ICs in a stack, said ICs including a first IC and a second IC, said first IC comprising a transistor layer with core circuits, a plurality of metal layers, a plurality of VIA layers and a first solder pad layer with a plurality of first solder pads and a plurality of dummy pads, said second IC comprising a transistor layer, a plurality of metal layers, a plurality of VIA layers and a second solder pad layer with a plurality of second solder pads, the multichip package manufacturing process comprising the steps of first IC production, first IC chip probing, second IC production, second IC chip proving, die sawing and bonding, wire bonding, packaging and final test to form an automotive IC package, wherein producing said first IC comprises the steps of:

• (C01) transistor layer production;
• (C02) first metal layer production;
• (C03) first VIA layer production;
• (C04) second metal layer production;
• (C05) second VIA layer production;
• (C06) third metal layer production;
• (C07) third VIA layer production;
• (C08) fourth metal layer production;
• (C09) fourth VIA layer production;
• (C10) fifth metal layer production;
• (C11) production of plural first solder pads and plural dummy pads of first solder pad layer;
• wherein steps C08˜C11 are performed by modifying at least one said metal layer, at least one said VIA layers and the plural said dummy pads for the configuration of said second pads of said second IC.