US 2022/0028475 A1 · ON-CHIP-COPY FOR INTEGRATED MEMORY ASSEMBLY

Abstract

A non-volatile memory system comprises an integrated memory assembly in communication with a memory controller. The integrated memory assembly includes a memory die bonded to a control die. The control die includes one or more control circuits for controlling the operation of the memory die. The control circuits are configured to receive a request to copy data on the memory die, read codewords on the memory die in response to the request, decode the codewords to identify errors in the codewords, correcting the errors in the codewords, and program the codewords back into the memory die. In one embodiment, the codewords read are stored in the memory die as single bit per memory cell data and the codewords programmed back into the memory die after correcting errors are programmed as multiple bit per memory cell data.

Claims20

Dependent claims

A method, comprising:

transferring codewords that are stored in non-volatile memory cells on a memory die to a control die bonded to the memory die, the codewords are stored in the non-volatile memory cells on the memory die as single bit per memory cell data;
on the control die, decoding the transferred codewords to identify one or more errors;
on the control die, fixing the identified errors in the codewords;
and
after fixing the identified errors in the codewords, programming the codewords to the memory die as multiple bit per memory cell data such that multiple non-volatile memory cells of the memory die store data from multiple codewords.

2 more elements

A method, comprising:

receiving a command from a memory controller to copy data stored on a first semiconductor die, the command is received at a second semiconductor die, the memory controller is connected to and separate from the second semiconductor die, the memory controller is also separate from the first semiconductor die, the second semiconductor die is bonded to the first semiconductor die;
in response to the command, transferring codewords from a first set of non-volatile memory cells on the first semiconductor to the second semiconductor die;
on the second semiconductor die, decoding the transferred codewords to identify one or more errors;
on the second semiconductor die, fixing the identified errors and creating updated codewords;
and
programming the updated codewords from the second semiconductor to non-volatile memory cells on the first semiconductor die.

3 more elements

A method, comprising:

receiving a request to copy data stored on a memory die, the request is received at a control die from a memory controller connected to and separate from the control die, the control die is bonded to the memory die, memory die includes non-volatile memory cells;
in response to the request to copy data, reading codewords from the memory die, the codewords are encoded versions of the data;
on the control die, decoding the transferred codewords to identify one or more errors;
on the control die, fixing the identified errors and creating updated codewords;
and
programming the updated codewords to the memory die;
the receiving the request, reading codewords, decoding, fixing and programming are performed without transferring the codewords to the memory controller.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/494,129Filed 5 Oct 2021

Priority

28 May 2020

Published

27 Jan 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 29/44
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: indication or identification of errors, e.g. for…
G11C 29/12005
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: comprising voltage or current generators
G11C 29/42
Response verification devices: using error correcting codes [ECC] or parity check
G11C 29/78
Masking faults in memories by using spares or by reconfiguring: using programmable devices

On-chip-copy for integrated memory assembly

Life of this patent

On-chip-copy for integrated memory assembly

Life of this patent

Abstract

Claims20