Memory device, integrated circuit device and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Sheng CHANG, Yao-Jen YANG
Life of this patent
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Abstract
A memory device includes at least one bit line, at least one source line, at least one program word line, at least one read word line, and at least one memory cell including a program transistor and a read transistor. The program transistor includes a gate terminal coupled to the at least one program word line, a first terminal coupled to the at least one source line, and a second terminal. The read transistor includes a gate terminal coupled to at least one read word line, a first terminal coupled to the at least one bit line, and a second terminal coupled to the second terminal of the program transistor.
Claims21
A memory device, comprising:
- at least one bit line;
- at least one source line;
- at least one program word line;
- at least one read word line;
- and
- at least one memory cell comprising a program transistor and a read transistor,
- wherein
- the program transistor comprises:
- a gate terminal coupled to the at least one program word line,
- a first terminal coupled to the at least one source line, and
- a second terminal, and
- the read transistor comprises:
- a gate terminal coupled to the at least one read word line,
- a first terminal coupled to the at least one bit line, and
- a second terminal coupled to the second terminal of the program transistor.
11-18. (canceled)
A method, comprising:
- in a programming operation of a first memory cell having a first program transistor,
- applying a higher, program voltage to a source/drain of the first program transistor, and
- applying a lower, reference voltage to a gate of the first program transistor, wherein a voltage difference between the program voltage and the reference voltage is equal to or higher than a predetermined breakdown voltage to break down a gate dielectric of the first program transistor.
A method, comprising:
- in a programming operation of a memory cell having a program transistor and a read transistor coupled in series to each other,
- causing a programing current to flow through the program transistor, without flowing through the read transistor;
- and
- in a read operation of the memory cell,
- causing a read current to flow through the program transistor and the read transistor.
Dependencies are inferred from the claim text.