Memory device

A memory device comprising:

• a variable resistance memory region extending in a first direction that is orthogonal to a semiconductor substrate;
• a semiconductor layer extending in the first direction and being in contact with the variable resistance memory region;
• an insulating layer extending in the first direction and being in contact with the semiconductor layer;
• a first word line extending in a second direction that is orthogonal to the first direction and being in contact with the insulating layer;
• a second word line extending in the second direction, being in contact with the insulating layer, and being located at a position different from the first word line in the first direction;
• a first select gate line extending in the second direction and being in contact with the insulating layer;
• and
• a bit line extending in a third direction that is orthogonal to the first direction and the second direction, and being in contact with the semiconductor layer,
• wherein
• in a first plane defined by the second direction and the third direction, a portion where the variable resistance memory region, the semiconductor layer, and the insulating layer intersect the first word line functions as a first memory cell,
• in the first plane, a portion where the variable resistance memory region, the semiconductor layer, and the insulating layer intersect the second word line functions as a second memory cell,
• in the first plane, a portion where the semiconductor layer and the insulating layer intersect the first select gate line functions as a first select transistor, and
• when information stored in the first memory cell is read, or when information is written into the first memory cell,
• after a voltage of the first select gate line, a voltage of the first word line, and a voltage of the second word line are set to a first voltage,
• the voltage of the first select gate line is increased from the first voltage to a third voltage higher than the first voltage,
• after at least the voltage of the first select gate line is increased to a second voltage between the first voltage and the third voltage,
• the voltage of the first word line and the voltage of the second word line are increased from the first voltage to a fourth voltage, and
• after the voltage of the first word line and the voltage of the second word line become the fourth voltage,
• the voltage of the first word line is decreased from the fourth voltage to the first voltage.

A memory device comprising:

• a variable resistance memory region extending in a first direction that is orthogonal to a semiconductor substrate;
• a semiconductor layer extending in the first direction and being in contact with the variable resistance memory region;
• an insulating layer extending in the first direction and being in contact, with the semiconductor layer;
• a first word line extending in a second direction that is orthogonal to the first direction and being in contact with the insulating layer;
• a plurality of second word lines extending in the second direction, being in contact with the insulating layer, being located at a position different from the first word line in the first direction, and being stacked in the first direction;
• a first select gate line extending in the second direction and being in contact with the insulating layer;
• and
• a bit line extending in a third direction that is orthogonal to the first direction and the second direction and being in contact with the semiconductor layer,
• wherein
• in a first plane defined by the second direction and the third direction, a portion where the variable resistance memory region, the semiconductor layer, and the insulating layer intersect the first word line functions as a first memory cell,
• in a first plane defined by the second direction and the third direction, a portion where the variable resistance memory region, the semiconductor layer, and the insulating layer intersect the second word lines functions as a plurality of second memory cells,
• in the first plane, a portion where the semiconductor layer and the insulating layer intersect the first select gate line functions as a first select transistor, and
• when information stored in the first memory cell is read, or when information is written into the first memory cell,
• after a voltage of the first select gate line, a voltage of the first word line, and voltages of the second word lines are set to a first voltage,
• the voltages of the second word lines are sequentially increased from the first voltage to a second voltage in order from a second word line at a longest distance from the first word line among the second word lines toward a second word line at a shortest distance from the first word line among the second word lines in the first direction.