Sense amplifier, memory and method for controlling sense amplifier

Abstract

A sense amplifier includes: an amplification circuit, configured to read data of a memory cell on a first bit line or a second bit line; and a first offset voltage storage cell and a second offset voltage storage cell, respectively and electrically connected to the amplification circuit, wherein in a case where the data in the memory cell on the first bit line is read, in an offset elimination stage of the sense amplifier, the sense amplifier is configured to store an offset voltage of the sense amplifier in the first offset voltage storage cell; and in a case where the data in the memory cell on the second bit line is read, in the offset elimination stage of the sense amplifier, the sense amplifier is configured to store the offset voltage of the sense amplifier in the second offset voltage storage cell.

Dependencies are inferred from the claim text.