Microprocessor core with a store dependence predictor accessed using a translation context

A processor that mitigates side channel attacks that exploit speculative store-to-load forwarding in a processor, the processor comprising:

• a store dependence predictor that predicts whether store data is or will be available and forwardable to a load instruction, wherein the store dependence predictor:
• is accessible using an identifier and TC of a load instruction;
• and
• generates a signal that reflects said prediction of whether store data is available and forwardable to the load instruction;
• wherein a TC comprises an address space identifier (ASID), a virtual machine identifier (VMID), a privilege mode (PM) or a translation regime (TR), a combination of two or more of the ASID, VMID, and TR or PM, or a hash and/or subset of the ASID, VMID, and/or TR or PM.

A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a processor for mitigating side channel attacks, the processor comprising:

• a store dependence predictor that predicts whether store data is or will be available and forwardable to a load instruction, wherein the store dependence predictor:
• is accessible using an identifier and TC of a load instruction;
• and
• generates a signal that reflects said prediction of whether store data is available and forwardable to the load instruction;
• wherein a TC comprises an ASID, VMID, PM or TR, a combination of two or more of the ASID, VMID, and TR or PM, or a hash and/or subset of the ASID, VMID, and/or TR or PM.