Widening memory access to an aligned address for unaligned memory operations
AssigneeMicrosoft Technology Licensing, LLC
InventorsDarek MIHOCKA, Arun Upadhyaya KISHAN, Pedro Miguel SEQUEIRA DE JUSTO TEIXEIRA
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AssigneeMicrosoft Technology Licensing, LLC
InventorsDarek MIHOCKA, Arun Upadhyaya KISHAN, Pedro Miguel SEQUEIRA DE JUSTO TEIXEIRA
Estimating the term…
Unaligned atomic memory operations on a processor using a load-store instruction set architecture (ISA) that requires aligned accesses are performed by widening the memory access to an aligned address by the next larger power of two (e.g., 4-byte access is widened to 8 bytes, and 8-byte access is widened to 16 bytes). Data processing operations supported by the load-store ISA including shift, rotate, and bitfield manipulation are utilized to modify only the bytes in the original unaligned address so that the atomic memory operations are aligned to the widened access address. The aligned atomic memory operations using the widened accesses avoid the faulting exceptions associated with unaligned access for most 4-byte and 8-byte accesses. Exception handling is performed in cases in which memory access spans a 16-byte boundary.
A method for performing unaligned atomic memory operations on a memory having a plurality of address boundaries by a processor that employs aligned access for an atomic memory operation to the memory, the atomic memory operation supporting a maximum of 2{circumflex over ( )}W bytes, the method comprising:
One or more hardware-based non-transitory computer readable memory devices storing computer-executable instructions which, upon execution by one or more processors in a computing device, cause the computing device to:
A computing device, comprising:
Dependencies are inferred from the claim text.