Efficient pipelined architecture for superconducting single flux quantum logic circuits utilizing dual clocks

A single flux quantum (“SFQ”) circuit system comprising:

• at least one SFQ block that includes a plurality of SFQ logic gates, at least a portion of the SFQ logic gates arranged in series;
• and
• an SFQ clock generator circuit, generating a first clock signal and a second clock signal, each signal comprising a regular stream of SFQ clock pulses, where the first clock signal is a fast clock signal operating at a fast clock frequency and the second clock signal is a slow clock signal operating at a slow clock frequency, the fast clock frequency being larger than the slow clock frequency, wherein inputs to and outputs of the at least one SFQ block are provided at a first rate defined by the slow clock frequency while the SFQ logic gates in the at least one SFQ block being clocked at a second rate defined by the fast clock frequency.

A single flux quantum (“SFQ”) circuit system comprising:

• at least one SFQ block that includes a plurality of SFQ logic gates, at least a portion of the SFQ logic gates arranged in series;
• and
• a timing system configured to provide a first set of inputs and collect a first set of outputs of the at least one SFQ block at a rate defined by a slow clock frequency while the SFQ logic gates are clocked at a fast clock frequency wherein the said rate is sufficiently slow to allow the first set of inputs to propagate through all levels of the SFQ logic gates to produce the first set of outputs of the at least one SFQ block without colliding with a second set of inputs to the at least one SFQ block.