Semiconductor devices

A semiconductor device, comprising:

• a substrate including a first region and a second region, which are spaced apart from each other with a device isolation layer interposed therebetween;
• a first gate electrode and a second gate electrode, which are respectively on the first region and the second region, are extended in a first direction, and are aligned with each other in the first direction, the first gate electrode comprising a first side and a second side that are opposing each other, and the second gate electrode comprising a first side and a second side that are opposing each other;
• an insulating separation pattern separating the first gate electrode and the second gate electrode from each other and extending in a second direction that traverses the first direction;
• a connection structure electrically connecting the first gate electrode to the second gate electrode;
• a first signal line electrically connected to the connection structure;
• a first source/drain region adjacent the first side of the first gate electrode;
• a second source/drain region adjacent the first side of the second gate electrode;
• a first active contact and a second active contact on the first source/drain region and the second source/drain region, respectively;
• a second signal line electrically connecting the first and second source/drain regions to each other, through the first and second active contacts;
• a third source/drain region adjacent the second side of the first gate electrode;
• a fourth source/drain region adjacent the second side of the second gate electrode;
• a first power rail electrically connected to the third source/drain region and extends in the second direction;
• and
• a second power rail electrically connected to the fourth source/drain region and extends in the second direction,
• wherein the first signal line extends in the second direction and vertically overlaps the insulating separation pattern.

A semiconductor device comprising:

• a unit cell comprising:
• a first active region and a second active region spaced apart from each other in a cell height direction;
• a first gate electrode and a second gate electrode vertically overlapping the first active region and second active region, respectively, wherein the first gate electrode and the second gate electrode are spaced apart from each other in the cell height direction and are colinear along the cell height direction;
• a connection structure that electrically connects the first gate electrode and the second gate electrode and vertically overlaps a portion of the first gate electrode and a portion of the second gate electrode;
• and
• a signal line electrically connected to the connection structure, wherein the signal line extends in a cell width direction and is between the first gate electrode and the second gate electrode in a plan view.