Gate-last ferroelectric field effect transistor and manufacturing method thereof

A ferroelectric field effect transistor, comprising:

• a substrate;
• isolation regions symmetrically arranged at two ends of the substrate, wherein upper surfaces of the isolation regions are not lower than an upper surface of the substrate, and bottom surfaces of the isolation regions are higher than that of the substrate;
• a gate structure arranged at a middle part of the upper surface of the substrate;
• a side wall spacer arranged outside the gate structure, wherein an inner surface of the side wall spacer is closely attached to the gate structure;
• source and drain regions, comprising a source region and a drain region which are formed by extending from inner sides of the isolation regions to the middle part of the substrate, wherein upper surfaces of the source region and the drain region are flush with the upper surface of the substrate, and bottom surfaces of the source region and the drain region are higher than those of the isolation regions;
• a first metal silicide layer formed by extending from the inner sides of the isolation regions to the side wall spacer, wherein an upper surface of the first metal silicide layer is higher than that of the substrate, a bottom surface of the first metal silicide layer is higher than those of the source and drain regions, and the first metal silicide layer is shorter than the source and drain regions;
• and
• an interlayer dielectric layer formed by extending from outer sides of the isolation regions to the side wall spacer, wherein an upper surface of the interlayer dielectric layer is flush with that of the side wall spacer, and a lower surface of the interlayer dielectric layer is closely attached to the upper surfaces of the isolation regions and the first metal silicide layer.