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US 2022/0020774 A1Published application
Memory device and method for fabricating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHan-Jong Chia, Meng-Han Lin, Yu-Ming Lin
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Abstract
A memory device including a word line, memory cells, source lines and bit lines is provided. The memory cells are embedded in and penetrate through the word line. The source lines and the bit lines are electrically connected the memory cells. A method for fabricating a memory device is also provided.
Claims20
A memory device, comprising:
- a word line;
- memory cells embedded in and penetrating through the word line;
- source lines electrically connected the memory cells;
- and
- bit lines electrically connected the memory cells.
2 more elements
A memory device, comprising:
- strip-shaped stacking structures each comprising conductive lines and dielectric patterns stacked alternately;
- pillar-shaped structures penetrating through the conductive lines and the dielectric patterns of the strip-shaped stacking structure, each of the pillar-shaped structures comprising:
- a first conductive pillar;
- a second conductive pillar;
- an isolation structure disposed between the first conductive pillar and the second conductive pillar;
- an oxide semiconductor layer and a charge storage dielectric layer, wherein the oxide semiconductor layer and the charge storage dielectric layer laterally surround the first conductive pillar, the second conductive pillar and the isolation structure, and the charge storage dielectric layer is disposed between the oxide semiconductor layer and one of the strip-shaped stacking structures;
- and
- signal lines electrically connected to the first and second conductive pillars.
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A method, comprising:
- forming a dielectric stack comprising first dielectric layers and second dielectric layers stacked alternately;
- forming through holes in the dielectric stack;
- filling each one of the through holes with a charge storage dielectric layer, a channel layer and an insulating material, wherein the channel layer is between the charge storage dielectric layer and the insulating material;
- patterning the dielectric stack to form first strip-shaped stacking structures, wherein each of the first strip-shaped stacking structures comprises first dielectric patterns and second dielectric patterns stacked alternately;
- removing the second dielectric patterns of the first strip-shaped stacking structures;
- forming conductive layers between the first dielectric patterns to form second strip-shaped stacking structures each comprising the conductive layers and the first dielectric patterns stacked alternately;
- after forming the second strip-shaped stacking structures, partially removing the insulating material in each one of the through holes to form an isolation structure and pillar-shaped apertures spaced apart from each other by the isolation structure;
- and
- forming source pillars and drain pillars in the pillar-shaped apertures.
6 more elements
Dependencies are inferred from the claim text.