Back Biasing of FD-SOI Circuit Block

A microelectronic circuit structure comprising:

• a stack of bonded layers including a bottom layer and at least one upper layer through direct bonding interconnect (DBI), the at least one upper layer comprising an oxide layer having a back surface and a front surface closer to the bottom layer than the back surface;
• a plurality of fully depleted silicon-on-insulator (FD-SOI) transistors built on the front surface of the oxide layer;
• and
• a plurality of back gate lines on the back surface of the oxide layer configured to provide back gate bias to the plurality of FD-SOI transistors, wherein each back gate line is electrically connected to a metal of an interconnection separated from the back gate lines by a passivation layer, wherein each back gate line is electrically connected to the metal through a single conductive pathway in the passivation layer.