US 2022/0020739 A1Published application

Semiconductor device

AssigneeRenesas Electronics Corporation

InventorYasuyuki MORISHITA

Life of this patent

Estimating the term…

Loading patent…

Abstract

A first ESD protection circuit is provided between a first high-potential side power supply and a first low-potential side power supply of a first power supply system and a second ESD protection circuit is provided between a second high-potential side power supply and a second low-potential side power supply of a second power supply system. A coupling circuit includes a bidirectional diode and couples the first and second low-potential side power supplies. A first transistor is composed of an n-channel MOS transistor, has a drain coupled to the first high-potential side power supply of the first power supply system, and has a back gate coupled to the second low-potential side power supply of the second power supply system. A resistor element is inserted in series between the drain of the first transistor and the first high-potential side power supply.

Claims13

Dependent claims

A semiconductor device including a first power supply system composed of a first high-potential side power supply and a first low-potential side power supply and a second power supply system composed of a second high-potential side power supply and a second low-potential side power supply, the semiconductor device comprising:

a first ESD protection circuit provided between the first high-potential side power supply and the first low-potential side power supply and configured to absorb an input surge;
a second ESD protection circuit provided between the second high-potential side power supply and the second low-potential side power supply and configured to absorb an input surge;
a coupling circuit including a bidirectional diode and configured to couple the first low-potential side power supply and the second low-potential side power supply;
a first transistor composed of an n-channel MOS transistor, having a drain coupled to the first high-potential side power supply, and having a back gate coupled to the second low-potential side power supply;
and
a first resistor element inserted in series between the drain of the first transistor and the first high-potential side power supply.

3 more elements

a first ESD protection circuit provided between the first high-potential side power supply and the first low-potential side power supply and configured to absorb an input surge;
a second ESD protection circuit provided between the second high-potential side power supply and the second low-potential side power supply and configured to absorb an input surge;
a coupling circuit including a bidirectional diode and configured to couple the first low-potential side power supply and the second low-potential side power supply;
a first transistor composed of an n-channel MOS transistor, having a drain coupled to the first high-potential side power supply, and having a back gate coupled to the second low-potential side power supply;
and
a first resistor element inserted in series between the back gate of the first transistor and the second low-potential side power supply.

3 more elements

a first ESD protection circuit provided between the first high-potential side power supply and the first low-potential side power supply and configured to absorb an input surge;
a second ESD protection circuit provided between the second high-potential side power supply and the second low-potential side power supply and configured to absorb an input surge;
a coupling circuit including a bidirectional diode and configured to couple the first low-potential side power supply and the second low-potential side power supply;
a first transistor composed of an n-channel MOS transistor, having a drain coupled to the first high-potential side power supply, and having a back gate coupled to the second low-potential side power supply;
and
a third ESD protection circuit provided between the first high-potential side power supply and the second low-potential side power supply and configured to absorb an input surge.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/349,547Filed 16 Jun 2021
Priority: JP 2020-12114115 Jul 2020
Published: 20 Jan 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10D 89/611
For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: using diodes as protective elements
H03K 17/6871
The devices being field-effect transistors: the output circuit comprising more than one controlled field-effect transistor
H10D 89/921
For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: characterised by the configuration of the interconnections connecting the…
H10D
Inorganic electric semiconductor devices