Tamper-resistant circuit, back-end of the line memory and physical unclonable function for supply chain protection

A tamper-resistant integrated circuit comprising:

• a substrate having a plurality of logic cells forming operative circuitry;
• a plurality of metal wiring layers located above said substrate at least some of which provide wiring for said operative circuitry, said metal wiring layers including a first metal wiring layer which is immediately above a second metal wiring layer;
• and
• a memory array of solid-state nonvolatile memory cells fabricated in a back-end of the line process and located between said first metal wiring layer and said second metal wiring layer, said first metal wiring layer and said second metal wiring layer having metal portions which together form a metal mesh having a spacing no greater than 1.3 micrometers that surrounds said memory array, wherein said substrate, said plurality of metal wiring layers and said memory array are part of a single monolithic structure, and said substrate includes measurement circuits for said solid-state nonvolatile memory cells, each measurement circuit having a differential sense amplifier which provides a constant current flow for memory cell measurement to prevent picosecond imaging circuit analysis of said solid-state nonvolatile memory cells.

A method of confirming identification of an integrated circuit chip comprising:

• receiving a request for chip identification at the integrated circuit chip from a chip identification system, wherein the integrated circuit chip has a tamper-resistant memory containing a physical unclonable function identifier that uniquely identifies the integrated circuit chip, an unencrypted release key, and an encryption key, and the request includes an encrypted release key;
• decrypting the encrypted release key using the encryption key to generate a decrypted release key;
• determining that the decrypted release key matches the unencrypted release key;
• and
• responsive to said determining, encrypting the physical unclonable function identifier using the encryption key and transmitting a response to the chip identification system, wherein the response includes the encrypted physical unclonable function identifier.