Eccentric Via Structures for Stress Reduction
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShu-Shen Yeh, Che-Chia Yang, Chia-Kuei Hsu, Po-Yao Lin, Shin-Puu Jeng, Chia-Hsiang Lin
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShu-Shen Yeh, Che-Chia Yang, Chia-Kuei Hsu, Po-Yao Lin, Shin-Puu Jeng, Chia-Hsiang Lin
Estimating the term…
A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.
A method comprising:
A structure comprising:
A structure comprising:
Dependencies are inferred from the claim text.