Semiconductor package and package-on-package including the same

A semiconductor package comprising:

• a support wiring structure;
• a semiconductor chip on the support wiring structure, the semiconductor chip having an upper surface positioned at a vertical level that is a reference level;
• a cover wiring structure on the semiconductor chip;
• a plurality of connection structures penetrating a filling member and configured to electrically connect the support wiring structure to the cover wiring structure, the plurality of connection structures are spaced apart from the semiconductor chip, and arranged around the semiconductor chip, each of the plurality of connection structures including a lower connection unit having an upper surface positioned at the reference level and extending below the reference level and an upper connection unit having a lower surface positioned at the reference level and extending above the reference level;
• and
• the filling member fills a space between the support wiring structure and the cover wiring structure, the filling member surrounding the plurality of connection structures and comprising a plurality of fillers,
• wherein a partial portion of the plurality of fillers comprises cutting fillers having an upper surface that is a flat surface that extends along the reference level.

A package-on-package comprising:

• a first semiconductor package comprising:
• a first printed circuit board (PCB);
• a first semiconductor chip on the first PCB and having an upper surface positioned at a vertical level that is a reference level;
• a second PCB on the first semiconductor chip;
• a filling member filling a space between the first PCB and the second PCB, the filling member surrounding the first semiconductor chip and containing a plurality of fillers;
• and a plurality of connection structures penetrating the filling member, the plurality of connection structures is configured to electrically connect the first PCB to the second PCB;
• and
• a second semiconductor package comprising:
• a second semiconductor chip;
• and a package connection terminal attached to a portion of a plurality of second wiring patterns and configured to electrically connect the second semiconductor chip to the first semiconductor package, the second semiconductor package is stacked on the first semiconductor package,
• wherein a partial portion of the plurality of fillers are cutting fillers having an upper surface that is a flat surface that extends along the reference level and a side surface that is a curved surface and is positioned at a vertical level that is lower than the reference level.